The present invention relates to a semiconductor device, and more specifically to a semiconductor device using an SOI (Silicon On Insulator) on substrate.
In the field of the power electronics, an IGBT (insulated gate bipolar transistor) which combines the convenience that the voltage can be driven by its gate, and a high output property of a bipolar transistor is available at the same time, is widely used. Due to the above-described advantages, such an IGBT is capable of controlling a larger current than by a power MOSFET.
FIG. 1 is a plan view illustrating the structure of a lateral-type IGBT of the above-mentioned type, taken at the interface between the electrode and semiconductor, and FIG. 2 is a cross sectional view taken along the line 2--2 of FIG. 1, with the electrode. In the present specification, the plan views are taken at the interface between the electrode and semiconductor, whereas the cross sectional views are illustrated with the electrode set on the transistor.
In the lateral-type IGBT, a buried oxide layer 2 of SiO2 and an n-type active layer 3 having a high resistance, are formed in the order on a silicon substrate 1. An approximately stripe-type n-type buffer layer 4 is formed selectively in the surface portion of the n-type active layer 3 such that the buffer layer 4 does not reach the buried oxide film 2. Thus, a p.sup.+ -type drain layer 5 serving as a p-type emitter layer is formed selectively in an approximately stripe-like manner, in the surface portion of the n-type buffer layer 4.
It should be noted that the n-type active layer 3 has a dose amount of about 1.times.10.sup.12 cm.sup.-2. The n-type buffer 4 is formed by the ion implantation of, for example, phosphorus, and has a dose amount of 5.times.10.sup.13 to 2.times.10.sup.14 cm.sup.-2. Further, the p.sup.+ -type drain layer 5 has a dose amount of 1.times.10.sup.15 cm.sup.-2 or more; however the dose amount may be 8.times.10.sup.14 cm.sup.-2.
Further, on the surface of the n-type active layer 3, which is different from the n-type buffer layer 4, an approximately stripe-shaped p-type base layer 6 is formed selectively such that it does not reach the buried oxide layer 2, and in the surface portion of the p-type base layer 6, a n.sup.+ -type source layer 7 and a p.sup.+ -type contact layer 8, each of which has a low resistance, are formed to have an approximately a stripe shape.
In the surface region from a portion of the n-type buffer layer 4 to the vicinity of the p-type base layer 6 in the n.sup.- -type active layer 3, a LOCOS oxide film 9 is formed, and on the region from an end of the n.sup.- -type active layer 3 located adjacent to the LOCOS oxide film 9 to a portion of the p-type base layer 6 and the n.sup.+ -type source layer 7, a gate oxide film 10 is formed.
A gate electrode 11 is formed on the gate oxide film 10, and an S-side field plate 12 which slightly extends from the gate electrode 11 towards the drain side, is formed on the LOCOS oxide film 9. In a similar manner, a D-side field plate 13 is formed in the vicinity of the n-type buffer layer 4 on the LOCOS oxide film 9.
On the p.sup.+ -type drain layer 5, a drain electrode 14 is formed to be in contact with a portion of the surface of the D-side field plate 13 as well. Further, a source electrode 15 is formed on the n.sup.+ -type source layer 7 and the p.sup.+ -type contact layer 8.
With the above-described structure, when a positive voltage is applied to the gate electrode 11, electrons appear on the surface of the p-type base layer 6 which is located directly underneath the gate such that the amount of electrons is proportional to the positive voltage, and the surface of the p-type base layer 6 is reversed to an n-type region. The reversed region becomes a channel, and thus the n.sup.+ -type source layer 7 and the n-type active layer 3 are short-circuited to each other.
Next, when a positive voltage is applied to the drain electrode 14 and a negative voltage is applied to the source electrode 15, electrons are supplied from the source electrode 15, and injected to the n.sup.- -type active layer 3 from the n.sup.+ -type source layer 7 via the channel. Thus, holes are injected from the p.sup.+ -type drain layer 5 to the n.sup.- -type active layer 3 via the n-type buffer layer 4. Due to the injection of the holes, a conduction modulation occurs, in which electrons and holes are present at high densities and they coexist substantially at the same density such as to cancel their electrical charges with each other. Consequently, the ON-state resistance is lowered, and the conduction state is established.
As a result, electrons in the n.sup.- -type active layer 3 flow to the drain electrode 14 via the p.sup.+ -type drain layer 5, whereas holes in the n.sup.- -type active layer 3 flow to the source electrode 15 via the p-type base layer 6.
In the meantime, at the time of turning OFF, a positive gate voltage is removed from the gate electrode 11. Consequently, a channel layer disappears on the surface of the p-type base layer 6 which is situated directly underneath the gate, and thus the n.sup.+ -type source layer 7 and the n.sup.- -type active layer 3 are shut off from each other, thus stopping the injection of the electrons. On the other hand, with regard to the holes in the n.sup.- -type active layer 3, some of them are discharged to the source electrode 15 via the p-type base layer 6, and the rest of them are recombined with electrons and extinguished. Thus, the lateral-type IGBT is turned off.
However, in an IGBT of the above-described type, holes which are minority carriers are injected to the n.sup.- -type active layer 3 so as to induce a conduction modulation, and thus the ON-state resistance is lowered. With this manner, even if the gate is shut off and the injection of electrons is stopped, a current still flows to the element while accumulated holes are being discharged. Therefore, such an IGBT entails a drawback that the switching rate is slow as compared to a power MOSFET. In order to solve this drawback, and improve the switching characteristics of a lateral-type IGBT, it is necessary to control the efficiency of the injection of holes from the drain.
The following are some of the examples, namely techniques (a) to (c) for controlling the injection efficiency.
(a) In this technique, a portion of the drain electrode 14 is contacted to the n.sup.- -type active layer 3. However, with this technique, holes are not sufficiently injected during the ON state, and therefore the ON-state characteristics are deteriorated.
(b) In this technique, the dose amount of the n-type buffer layer 4 is increased. The details will now be described with reference to the curve N shown in FIG. 3. The curve N indicates the trade off between an ON voltage Vf and a turn-off time Tf while the dose amount of the n-type buffer layer 4 is varied. As can be understood from the curve N, this technique is effective for the improvement of the switching rate up to about 500 ns; however it cannot be applied in practice for the manufacture of a lateral-type IGBT having a turn-off time Tf of that rate or less since the dose amount of the n-type buffer layer 4 exceeds 1.times.10.sup.15 cm.sup.-2, and the ON voltage becomes very high in such a case.
(c) This technique is an improved version which has been proposed to solve the drawback of the technique (b), and in this technique, the dose amount of the n-type buffer layer 4 is maintained as it is, and the dose amount of the p.sup.+ -type drain layer 5 is decreased. With this technique, as can be understood from the curve P in FIG. 3, and the illustration of FIG. 4, the turn-off time Tf can be improved to about 300 ns; however in the case where the turn-off time is set at 300 ns or less, it becomes necessary to decrease the surface concentration of the p.sup.+ -type drain layer 5. When the surface concentration becomes 1.times.10.sup.19 cm.sup.-3, it becomes very difficult to make an ohmic contact. As a result, a Schottky barrier occurs and the contact resistance is increased. Consequenty, the ON-state voltage Vf is increased, which is not desirable.
As described above, the lateral-type IGBT entails the drawback of a long turn-off time Tf. However, if the turn-off time is shortened, another problem of an increase in the ON-state voltage Vf occurs. Further, with such an increase in the ON-state voltage Vf, the output characteristics are deteriorated, and the electrical current value which enables the operation is lowered.